It is conventional for modern electronic devices such as smartphones to include a plurality of interconnected integrated circuits. For example, a smartphone may include an application processor that interfaces with other integrated circuits such as sensors and baseband circuits. To save power, it is also conventional for these various integrated circuits to be independently operated such that one integrated circuit may be powered down in a deep sleep mode of operation while another integrated circuit continues to operate in a normal mode of operation. Although this independent operation of integrated circuits saves power, it raises the issue of reverse current generation.
To better appreciate the reverse current problem, note that the power supply rail for an integrated circuit's input/output (I/O) buffers will typically be protected by an electrostatic discharge (ESD) diode that couples from a buffer's I/O pad or terminal to the internal buffer power supply rail. Should an electrostatic discharge present a sudden application of positive voltage on the I/O terminal, the ESD diode becomes forward biased and safely discharges the electrostatic charge to the power supply rail. But suppose that the corresponding integrated circuit that includes the I/O terminal is powered down while another integrated circuit that interconnects to the I/O terminal is still operating. This additional integrated circuit may have a default mode in which it maintains the lead coupling to the I/O terminal at a positive voltage. The ESD diode will then be forward biased such that the power supply rail coupled to the I/O terminal will be charged to the positive voltage on the lead (minus a threshold voltage drop for the forward-biased ESD diode). The PMOS transistors in the integrated circuit having their sources coupled to the buffer power supply rail would then be conducting since their gates would be discharged due to the off state of the integrated circuit. Not only does this waste power but it also leads to erroneous operation or faults upon a subsequent powering up of the integrated circuit.
To address the reverse current problem, various approaches have been developed. For example, an integrated circuit such as an applications processor may be programmed to be aware of the state of other integrated circuits in the system. Should another integrated circuit be powered down, the processor would then discharge any leads it has that couple to I/O terminals on the powered-down integrated circuit. But such an approach burdens the user with having to program the processor accordingly. In another approach, external components may also be located in the signal path between integrated circuits to gate signals when an interconnected integrated circuit is powered down. Such external components increase manufacturing costs. Alternatively, an integrated circuit may be configured with a head switch that is switched off when the integrated circuit is powered down. This typically requires additional terminals and control signals, which raises manufacturing costs and complicates the design.
Accordingly, there is a need in the art for improved reverse current protection circuits.